The invention relates to microprocessors and similar machines and specifically to an improvement in the arithmetic units of such machines.
It is known in microprocessors to add bcd (binary coded decimal) operands in a parallel, straight binary adder and to then correct the sum so as to obtain a result which is in binary coded decimal form. Specifically, it is known that when the binary number 0110, which is the decimal number 6, is added to a 4-bit binary number the result is the binary coded decimal equivalent of that 4-bit binary number (plus a possible decimal carry). Based on this operation, it is possible for a microprocessor to have only a binary adder and to use the same straight binary adder to provide a binary coded decimal sum of the operands supplied to it by adding 0110 to each 4 bits of the sum from the adder (while accommodating carries). For example, a binary coded decimal sum is obtained in the prior art by adding two bcd operands in a parallel binary adder and then recycling the sum through the same binary adder as one operand while using 0110 as the other operand for each 4 bits (and taking carries into account). It is also known that the binary coded decimal difference of two bcd operands can be obtained by adding 1010, which is the decimal number 10, to the sum of the operands (and keeping track of carries). In a prior art example, this is again done by adding the two operands in a binary adder and recycling the resulting sum through the adder as one operand of a straight binary addition operation whose other operand is 1010 for each 4 bits.
It takes two cycles of the binary adder in each of these prior art operations to get the binary coded decimal sum or difference of two bcd operands: one cycle to get the binary sum and another to add a fixed binary number to the binary sum so as to get the binary coded decimal sum or difference of the original operands.
It is desirable in microprocessors to improve the speed by reducing the number of cycles necessary to perform a given operation. However, it is also desirable to have a minimum number of components, and it is typically not justified to have both a binary and a decimal adder in the same microprocessor. The prior art has typically chosen the disadvantage of using two cycles to get a decimal sum or difference rather than to suffer the cost of a separate decimal adder.
This invention takes a new approach to the problem: it uses only a binary adder to get the decimal sum or difference of two numbers, but does it in a single cycle of the binary adder, thus significantly improving the speed of operation without suffering the cost of an additional decimal adder. In accordance with the invention, the binary sum of two bcd operands is corrected by suitable gating as it travels from the binary adder to another part of the microprocessors, e.g., the accumulator, so that it becomes the binary coded decimal sum or difference of the two operands by the time it reaches that other part of the microprocessor.
More specifically, the invention is implemented in a machine, such as a microprocessor, which has a source of two binary or bcd operands, such as two registers, a binary adder, a source of a command for selectively performing decimal addition or decimal subtraction of the operands, and a destination for the binary or decimal sum or difference of the operands, such as an accumulator. In response to a command for decimal addition or decimal subtraction of the operands, suitable gating is activated to change certain adder carry bits from binary to decimal carries, and the output of the binary adder is modified by other gates to change selected bits of the binary sum such that the number delivered to the accumulator is the decimal sum or difference of the operands rather than the straight binary sum thereof.
In one specific embodiment of the invention, two 8-bit operands are applied to a parallel 8-bit binary adder. The binary carry from the low 4-bit section of the adder is changed by suitable gating to become a decimal carry, while the sum provided by the adder is corrected by other suitable gates as it travels toward the accumulator to change it to the binary coded sum or difference of the operands. The binary carry from the high order 4-bits of the binary adder is corrected to become a decimal carry which may be supplied to other portions of the microprocessor. The low 4-bits section of the binary adder can receive a carry-in from other parts of the microprocessor.